The present invention relates to a method of fabricating a semiconductor device. In particular, the present invention relates to a method of fabricating a semiconductor device including the steps of forming a conductive layer made from a high melting point metal based material (for example, a high melting point metal or a silicide thereof) on a semiconductor substrate; forming an opening portion; and forming a semiconductor layer in the opening portion at which a side surface of the conductive layer made from the high melting point metal or the silicide thereof is exposed. The present invention is applicable to a method of fabricating a semiconductor device containing, for example, a bipolar transistor, and particularly to a technique of forming a semiconductor layer, for example, taken as a base layer by selective epitaxial growth.
In recent years, there have been demands toward larger scale integration and higher performance of semiconductor devices typically LSIs. For example, there have been strong demands, particularly, toward higher-speed bipolar transistors.
In general, very high-speed bipolar transistors adopt a double silicon structure in which each of an emitter and a base extension electrode is made from poly-silicon. In this structure, an emitter electrode is isolated from a base electrode by a side wall insulating film, to thereby significantly reduce a base-collector capacitance.
In order to develop a higher-speed bipolar transistor, it is essential to form a heavily doped and thinned base layer. According to related art methods, however, it has been not necessarily easy to obtain a desirable base layer. For example, according to related art ion implantation techniques, it has been difficult to develop a base width of 40 nm or less because of channelling of an implanted impurity.
To solve the problem above, there has been known a method of forming a base layer forming film by epitaxial growth with no channeling. A heavily doped and thinned base layer having a base width of typically 30 nm or less has been formed by doping an impurity in the layer during epitaxial growth. Such a technique has realized a high-speed bipolar transistor having a maximum cutoff frequency of fT.sub.max =50 GHz and a maximum oscillation frequency f.sub.max =30 GHz or more.
Further, the dose of an impurity doped in a base layer can be increased by use of a base layer made from SiGe having a band gap smaller than that of Si. This reduces a base resistance, allowing realization of a high-speed bipolar transistor having a f.sub.max = about 50 GHz.
An internal base resistance is reduced by the above-described technique using a base layer made from SiGe by epitaxial growth; however, to develop a very high-speed bipolar transistor, it is necessary to reduce an external base resistance. To reduce a resistance of a base electrode, an attempt has been made to replace a poly-silicon structure of a base electrode with a silicide structure using, for example, a high melting point metal or a polycide structure which is a stacked structure of poly-silicon and a silicide. As a silicide material, there has been often used WSi which has been known as a gate electrode material for a MOS transistor, or the like. The use of WSi as the silicide material is effective to develop a BiCMOS in which a base electrode and a gate electrode are formed at the same step.
A related art method of using a base electrode of a polycide structure has been proposed, for example, in Japanese Patent Laid-open No. Hei 5-74789. This document discloses a process of fabricating an NPN transistor having a double poly-silicon structure using a stacked structure of poly-silicon and a silicide of a high melting point metal.
The technique disclosed in the above document, however, has a problem that there may occur contamination due to the silicide of the high melting point metal used for the fabrication process. To be more specific, upon formation of a layer in an opening portion by epitaxial growth, the interior of a chamber may be contaminated by the silicide of the high melting point metal exposed at the opening portion, leading to a possibility of occurrence of crystal defects in the epitaxial growth layer.
The problem above will be described in detail with reference to FIGS. 6 to 8. FIGS. 6 to 8 are sectional views of structures of a semiconductor device sequentially formed by steps of a related art method of fabricating a semiconductor device.
As shown in FIG. 6, an oxide insulating film 2 (SiO.sub.2 in this example) having a thickness of, for example, 30 nm is formed over the entire surface of a semiconductor substrate 1 (silicon substrate in this example) by thermal oxidation.
A semiconductor layer 3 (poly-silicon film in this example) having a thickness of 100 nm is formed by CVD performed at about 650.degree. C. using for example a SiH.sub.4 based gas, and further, a silicide film 4 (WSi film in this example) having a thickness of 80 nm is formed over the entire surface by CVD performed at about 700.degree. C. using for example a WF.sub.6 /H.sub.2 based gas. Then, ions of, for example, BF.sub.2 are implanted at 30 keV in a dose of 5.times.10.sup.-15 cm.sup.-2, to form a P-type polycide.
Next, an insulating film 5 (silicon nitride film, particularly, Si.sub.3 N.sub.4 film in this example) having a thickness of 150 to 200 nm is formed over the entire surface by for example CVD. Then, these films are patterned using a photoresist having an opening portion at a position of an emitter forming portion. To be more specific, the insulating film 5 (Si.sub.3 N.sub.4 film) in the opening portion is removed by RIE (Reactive Ion Etching) using for example a O.sub.2 /CHF.sub.3 based gas, and the silicide/semiconductor layer (WSi/poly-silicon) in the opening portion is removed by RIE using for example a SF.sub.6 /C.sub.2 Cl.sub.2 F.sub.3 gas.
Then, the oxide insulating film 2 (SiO.sub.2) under the semiconductor layer 3 (poly-silicon) is side-etched to a depth of about 50 nm by, for example, isotropic etching using diluted hydrofluoric acid or the like, to thus obtain a structure shown in FIG. 6 in which a side surface portion of the semiconductor layer 3 (poly-silicon) is overhung. In FIG. 6, the overhung portion is indicated by reference numeral 3'.
Referring to FIG. 7, after H.sub.2 -cleaning at 900.degree. C. for 5 min, an epitaxial growth layer 6 (thickness: about 10 to 50 nm, dose of boron: 1.times.10.sup.-18 to 3.times.10.sup.-19 cm.sup.-2) is formed by selective epitaxial growth performed, for example, at 850.degree. C. under a reduced pressure of several tens Torr, using for example a (SiH.sub.2 Cl.sub.2 +HCl) based gas. The epitaxial growth layer 6 is taken as a base layer 6. At this time, a poly-silicon film 7 grows at the above overhung portion of the side surface of the semiconductor layer 3 (poly-silicon).
Next, as shown in FIG. 8, a SiO.sub.2 film as an insulating film is formed by CVD using, for example TEOS (tetraethylorthosilane) as a source gas, followed by etching-back, to form a side wall 8. The side wall 8 acts to isolate an emitter from a base.
Then, a semiconductor layer 9 (poly-silicon layer in this example) having a thickness of 150 nm is formed by CVD performed at about 650.degree. C. using for example a SiH.sub.4 gas, followed by ion implantation of for example N.sup.+ ions and heat-treatment, to form an emitter diffusion layer 10. After that, respective electrodes are formed using the known various interconnection forming techniques.
The above-described related art method of fabricating a bipolar transistor, however, has the following problem.
In the above-described related art method, as shown in FIGS. 6 and 7, particularly, in FIG. 7, the film 4 of the silicide (tungsten silicide in the above example) of the high melting point metal is exposed at the emitter opening portion (the exposed portion is indicated by reference numeral 4' in FIG. 7). As a result, there is a possibility that upon selective epitaxial growth or upon pre-treatment thereof, that is, cleaning treatment, a chamber atmosphere is contaminated by the metal. The contamination of the chamber atmosphere may cause crystal defects in the epitaxial layer, leading to reduction in yield of semiconductor devices as products. Such a problem occurs in the case where any one of treatments for forming a semiconductor layer in an opening portion is performed in a state in which a high melting point metal based material such as a high melting point metal or a silicide thereof is exposed at the opening portion.